A serial access memory is used for serial data storing, or data conversion from serial to parallel and vice versa. FIG. 1 is a schematic block diagram illustrating a conventional circuit for controlling a serial access memory (SAM).
This conventional circuit includes an address buffer 1 for separating an input address into a row address (X address) and a column address (Y address); an X address decoder 7 for decoding the X address to select a word line; a Y address decoder 2 for decoding the Y address to generate sequential switching signals; an I/O control buffer section 10 for converting serial data into parallel data and vice versa; a data bus 15 connected to I/O section 10; a sequential transmitting switch 11 connected to the data bus; a plurality of first serial access registers 8 connected to the sequential transmitting switch; a first transmitting switch 12 connected to the first registers; for transmitting data to a plurality of second serial access registers 9 connected thereto; a second transmitting switch 13 connected to the second registers for transmitting data to a memory cell array 14; a transmission control section 4 for generating control signals to turn on and off the first and second transmitting switches; a first register control section 5 for controlling the power source for the first register; a second register control section 6; a read/write control section 3 for supplying control signals to first and second register control sections 5 and 6; and memory cell array 14 for writing and reading data to and from a bit line connected to the second transmission switch 13.
When reading the data, the row and column addresses are separated into X and Y addresses. The X address is decoded by X address decoder 7, and one of word lines WL.sub.1 -WL.sub.n are selected. The Y address is decoded by Y address decoder 2, and there is selected a proper switch set from among transmission switches which are connected between serial access register 8 and data bus 15.
The input and output of data between memory cell array 14 and data input/output line 16 is carried out in the following manner. When reading data, the output of X address decoder 7 selects a word line in accordance with the value of the X address. The cell data of memory cell array 14 which is connected to the specified word line is transmitted to second register 9, the word line being selected when second transmission switch 13 is turned on. Then first transmitting switch 12 is turned on, so that the data of the second register is transmitted to and stored in first register 8.
As Y address decoder 2 decodes the Y address to turn on transmitting switches 11 in a sequential manner, the data in first register 8 is transmitted in a parallel manner to input/output control buffer section 10. This parallel data is converted into perfect serial data by input and output control buffer section 10, and output through data I/O line 16.
To carry out a write operation, the serial data input through data I/O line 16 is converted into parallel, and loaded onto data bus 15. At the same time, in accordance with the Y address decoded by Y address decoder 2, appropriate transmitting switches are selected and turned on. The data on bus 15 is then transmitted to and stored in first register 8. When this register is filled, first transmitting switch 12 is turned on, so that second register 9 is then filled with the data. Then the X address decoder decodes the X address to select a word line, and, when the second transmitting switch 13 is turned on, the data in the second register is transferred to the memory cells which are connected to the selected word line.
In order to show the data transmission procedure between memory cell array 14 and data bus 15, FIG. 2 illustrates a conventional serial access memory control circuit connected between a pair of bit lines and a pair of data bus lines.
The conventional serial access memory control circuit of FIG. 2 usually includes a data bus 151 having a plurality of pairs of data bus lines DB and /DB, and this data bus 151 and first register 81 are inter-connected through transmission switches 111. Transmission switches 111 are controlled by a Y-DECOUT signal, while first register 81 is connected to register control section 51, so that the supplied power source can be controlled.
Further, first register 81 and second register 91 are inter-connected through transmission switch 121, and second register 91 is also connected to second register control section 61, so that the supplied power source can be controlled. Second register 91 is also connected to memory cell array 141 through transmission switch 131.
In other words, two cells which are connected from memory cell array 141 to word lines WL1 and WL2 are also connected to bit lines BL and /BL. Further, they are connected to second register 91 through second switch 131 which is controlled by signal TR2. Second register 91 usually consists of two NMOS transistors and two PMOS transistors. The second register is connected to first register 81 through first transmission switch 121 which is controlled by signal TR1. First register 81 is connected through a sequential transmitting switch 111 to data bus 151. The power source for first register 81 is controlled by first register control section 51. Further, first and second register control sections 51 and 61 are controlled by control signals RE1 and RE2 of R/W control section through two stages. Specifically, they are controlled to be in a low impedance state (turned on) or to a high impedance state (turned off).
In the circuit of FIG. 2, the data flow during the read/write operations is as described above referring to FIG. 1. Here, only the on/off timings of respective switches 111,121 and 131 during the read/write operations, and the enable timings of first and second registers (serial access memory registers) 81 and 91 will be described, with reference to the timing chart of FIG. 3.
When carrying out a read operation, word lines WL1 and WL2 are selected, and, thus, if a voltage is supplied, the transistor of the relevant cell is turned on. Then the charge of the cell capacitor is distributed to bit lines BL and /BL, and, accordingly, the data from the cell can be read by a sense amplifier. The voltage distribution of bit lines BL and /BL becomes as shown in FIG. 3. Signal RE2 (which is used for controlling the power source for the second register) is then generated by R/W control section 3 with a high level. As a result, the PMOS transistor is turned off, and therefore, the second register 91 is put in a floating state. At the same time, control signal TR2 becomes high (control signal TR2 is a control signal of second transmission switch 131 which connects bit lines BL and /BL of first register 81 to bit lines A and /A respectively of the second register 91) with the result that the voltages of bit lines BL and /BL are stored into the second register 91. Therefore, even when the operation of the word line and the sense amplifier stop, the cell data is stored in the second register. Signal RE1 (which controls the power source for the first register) then becomes high, and at the same time, control signal TR1 of first transmission switch 121 becomes high to connect bit lines A and /A of the second register 91 to bit lines B and /B of the first register 81, with the result that the voltages of bit lines A and /A are stored into the first register 81.
Output signal Y-DECOUT of the Y decoder (which is a signal for controlling transmission switch 111) then becomes high, so that the data bus is connected to bit lines B and /B of the first register. Consequently, the data of the first register is transmitted through bit lines B and /B to data buses DB and /DB respectively.
When carrying out a write operation, output signal Y-DECOUT of the Y becomes high, so that the data loaded on data buses DB and /DB is transmitted to the first register. Meanwhile, signals RE1 and RE2 become low, so that power is applied to the first and second registers. In this state, signal TR1 becomes high, so that the voltages of bit lines B and /B1 are stored into the second register. Then word lines WL1 and WL2 are selected to supply the voltage to turn on the transistor of the relevant cell, so that the voltages of bit lines BL and /BL can be supplied to the cell capacitor. Then signal becomes high to connect bit lines B and /B to bit lines A and /A of the second register, with the result that the voltages of bit lines A and /A of the second register are stored into the cell capacitor. Thereafter, the voltage of the word line is removed, so that the transistor of the cell is turned off, and the capacitor charge is maintained.
In the conventional serial access memory control circuit described above, when carrying out a read operation, signal RE2 is made to be high at the time when the data is transmitted from memory cell array 141 to second register 91. Thus second register (REG2) 91 is put in a floating state, to smoothen data transmission. Otherwise, signals RE1 and RE2 are made to be low, so that first and second registers 81 retain their data.
When carrying out a write operation, signals RE1 and RE2 are maintained at a low level, so that the power is supplied to both first and second registers 81 and 91 all the time.
Therefore, in the conventional serial access memory control circuit of FIG. 2, one PMOS transistor is utilized, so that when control signals TR1 and TR2 for the transmission switch become high, signals RE1 and RE2 also become high. The reason why the power source for the registers is turned off to put them in a floating state at the time when the data is transmitted is as follows. In order to transmit the data in a sure manner, the impedance of the power source at the receiving side is increased, and the power of the transmitting side is made to dominate the power of the receiving side, so that the data receiving side is subordinated to the transmitting side.
However, in the conventional serial access memory control circuit, the serial accessing registers are controlled to be floating at transmitting time. Therefore, the power source is momentarily disconnected from the register, with the result that the voltage states of bit lines A and /A and B and /B can become unstable. Further, the power sources are turned on and off almost simultaneously, and therefore, the voltage state of the respective nodes of the registers becomes unstable, and considerably high on/off noises are generated, so that the transmitted data can be corrupted. This also causes the stabilizing time for the transmission speed to increase.